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ADE7754
Table VIII. Register List (continued)
Address
Default
[A5:A0] Name
R/W * Length
Value
Description
13h
LINCYC
R/W
16
FFFFh
Line Cycle Register. The content of this register sets the number of half line
cycles while the active energy and the apparent energy are accumulated in the
LAENERGY and LVAENERGY registers. See the Energy Calculation section.
14h
SAGCYC
R/W
8
FFh
SAG Line Cycle Register. This register specifies the number of consecutive half
line cycles where voltage channel input falls below a threshold level. This regis-
ter is common to the three-line voltage SAG detection. The detection threshold
is specified by SAGLVL register. See the Line Voltage SAG Detection section.
15h
SAGLVL
R/W
8
0
SAG Voltage Level. This register specifies the detection threshold for
SAG event. This register is common to the three-line voltage SAG
detection. See the description of SAGCYC register for details.
16h
VPEAK
R/W
8
FFh
Voltage Peak Level. This register sets the level of the voltage peak
detection. If the selected voltage phase exceeds this level, the PKV flag
in the status register is set. See Table XII.
17h
IPEAK
R/W
8
FFh
Current Peak Level. This register sets the level of the current peak detec-
tion. If the selected current phase exceeds this level, the PKI flag in the
status register is set. See Table XII.
18h
GAIN
R/W
8
0
PGA Gain Register. This register is used to adjust the gain selection for
the PGA in current and voltage channels. See the Analog Inputs section
and Table X. This register is also used to configure the active energy
accumulation no-load threshold and sum of absolute values.
19h
AWG
R/W
12
0
Phase A Active Power Gain Register. The active power caluation for Phase A
can be calibrated by writing to this register. The calibration range is 50%
of the nominal full-scale active power. The resolution of the gain adjust is
0.0244%/LSB.
1Ah
1Bh
1Ch
BWG
CWG
AVAG
R/W
R/W
R/W
12
12
12
0
0
0
Phase B Active Power Gain.
Phase C Active Power Gain.
VA Gain Register. This register calculation can be calibrated by writing
this register. The calibration range is 50% of the nominal full-scale real
power. The resolution of the gain adjust is 0.02444%/LSB.
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
BVAG
CVAG
APHCAL
BPHCAL
CPHCAL
AAPOS
BAPOS
CAPOS
CFNUM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12
12
5
5
5
12
12
12
12
0
0
0
0
0
0
0
0
0h
Phase B VA Gain.
Phase C VA Gain.
Phase A Phase Calibration Register.
Phase B Phase Calibration Register.
Phase C Phase Calibration Register.
Phase A Power Offset Calibration Register.
Phase B Power Offset Calibration Register.
Phase C Power Offset Calibration Register.
CF Scaling Numerator Register. The content of this register is used in
the numerator of CF output scaling.
26h
CFDEN
R/W
12
3Fh
CF Scaling Denominator Register. The content of this register is used in
the denominator of CF output scaling.
27h
28h
29h
WDIV
VADIV
AIrms
R/W
R/W
R
8
8
24
0
0
0
Active Energy Register Divider.
Apparent Energy Register Divider.
Phase A Current Channel RMS Register. The register contains the rms
component of one input of the current channel. The source is selected
by data bits in the mode register.
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
BIrms
CIrms
AVrms
BVrms
CVrms
AIrmsOS
BIrmsOS
R
R
R
R
R
R/W
R/W
24
24
24
24
24
12
12
0
0
0
0
0
0
0
Phase B Current Channel RMS Register.
Phase C Current Channel RMS Register.
Phase A Voltage Channel RMS Register.
Phase B Voltage Channel RMS Register.
Phase C Voltage Channel RMS Register.
Phase A Current RMS Offset Correction Register.
Phase B Current RMS Offset Correction Register.
REV. 0
–33 –
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